The invention relates to techniques for etching layered materials to produce features in one or more of the layers, especially features having vertical walls and beveled edges, such as wells in a silicon oxide layer employed in integrated circuit fabrication to provide access through the layer to a substrate underlying the layer.
Developments in integrated circuit technology have resulted in the fabrication of devices with increasing numbers of layers, smaller features and increasing complex electrical interconnections. It is conventional to form a layer of silicon dioxide over the device, for example, to isolate it from the environment or interconnection conductors, and to etch wells in the silicon dioxide layer through which electrical interconnections are made to selected regions of the device. Typically the interconnections are one or more layers of metal evaporated or sputtered onto the silicon oxide and into the wells to form the desired interconnect pattern. As feature size is reduced, it becomes increasingly important to employ fabrication techniques such as anisotropic etching which form sharp well edges at locations defined by an overlying mask. However, these techniques can result in the formation of corners or steps in the well wall profile which are difficult to cover with overlying layers, particularly when the overlying layer is an evaporated or sputtered metal coating. As the surface topology becomes more complex with the formation of additional layers, the problem of step discontinuities in overlying layers is aggravated.
It is known in the prior art to round edges of silicon dioxide layers by a technique known as "reflowing" which involves the softening or melting of the silicon dioxide after the wells have been formed. However, this technique requires heating of the oxide to a temperature on the order of 1000.degree. C., and, thus may result in degradation of the device, for example, by diffusion of impurities from the oxide into the underlying structures or by redistribution of dopants in the substrate.
Other prior art techniques depend on the erosion of photoresist films to taper side walls of the wells. Unfortunately, uniform slopes cannot be obtained on many integrated circuit wafers since thickness and chemical composition, hence, etching rates, in the various areas of the circuit can differ significantly.
Isotropic plasma etching methods normally produce steep, undercut side walls with sharp corners and, in many applications, do not provide sufficient selectivity over silicon substrates.
In contrast, wet chemical etching can provide selectivity over silicon substrates, but also can undercut masking layers. Attempts to improve edge profiles with resist lifting agents, rapidly etched taper controlling films, and implantation damaged layers, may result in difficulties in controlling the size of the feature or well.
Accordingly, it is an object of the present invention to produce etched features which reduce step discontinuities in deposited layers overlying the etched layer features.
It is another object of the present invention to reduce step discontinuities in deposited metal layers overlying a silicon oxide layer with features etched therein, while preserving the desired size of the etched feature.
It is another object of the present invention to reduce such step discontinuities while providing substantially vertical feature walls, sharply defined by an overlying mask.
It is another object of the present invention to provide an etched feature wall in a silicon oxide layer with an improved profile.
It is another object of the present invention to provide an etched feature wall in a silicon oxide layer having horizontal dimensions which are substantially independent of oxide thickness, composition and surface topology.
It is another object of the present invention to provide etching techniques for producing features in a silicon oxide layer with substantially vertical walls intersecting a horizontal silicon substrate, without substantially etching the underlying silicon substrate.
These and other objects and features will be apparent from this application including the appended claims and drawings.